From Research to Reality: How OpenHW Foundation cores are building Europe's Open RISC-V Ecosystem

 

The European TRISTAN project (Together for RISc-V Technology and ApplicatioNs) has recently drawn to a close after three-and-a-half years of outstanding technical development and deployment. The first of a number of planned projects focusing on RISC-V technology, TRISTAN set the stage for future semiconductor research, development, and growth in Europe.

The OpenHW Foundation was part of the project from the outset, providing industry grade verification and consultation, building Europe’s first-ever RISC-V IP catalog, and leading technical communications. Today, we wanted to reflect on some of TRISTAN’s biggest achievements: developing an outstanding collaborative ecosystem of shared, open source innovations, and demonstrating that open-source processor IP is ready for real industrial applications.

Why European RISC-V?

TRISTAN set out to establish the foundations of a sustainable European silicon ecosystem where organisations can collaborate on trusted, high-quality open source hardware, reducing dependence on proprietary processor architectures while strengthening Europe's technological sovereignty. 

Funded by the European Chips Joint Undertaking programme, TRISTAN brought together 46 industrial, academic and research partners with a common goal: to accelerate the development of an open European RISC-V ecosystem spanning processors, software, design tools, verification environments and complete application platforms.

Semiconductors are strategic infrastructure. Like all critical technology systems, they are also at risk from geopolitical shifts, rising tariffs, and restrictions on usage. Therefore, European industries are increasingly turning to processors that are transparent, auditable, extensible and free from vendor lock-in. Open source hardware built around the RISC-V instruction set enables organisations to innovate collaboratively while retaining control over the technology that powers their products.

Building on Open Foundations

The OpenHW Foundation develops and stewards industrial-quality open source processor IP for commercial deployment. Throughout TRISTAN, the OpenHW CORE-V family became one of the project's foundational technologies. Across research and industrial sectors including energy, automotive, aerospace, industrial automation, communications, AI acceleration, and functional safety, partners repeatedly selected OpenHW processors as the building blocks for their demonstrators and, in many cases, their future commercial platforms.

Partners made extensive use of, and contributions to, OpenHW cores and platforms including: 

Europe’s First RISC-V IP Catalog 

One of the greatest achievements of TRISTAN is that it established a collaborative ecosystem where innovations are available to everyone. The European Unified RISC-V IP Access Platform (UAP), created by the TRISTAN consortium and hosted by the OpenHW Foundation provides a single source of verified, industry ready RISC-V components under various licenses from TRISTAN, ISOLDE and other European research projects. OpenHW is invested in stewarding this resource for years to come, ensuring that verified RISC-V IP is easily discoverable and adoptable. 

Technological sovereignty does not necessitate every organisation building independently. By creating trusted shared foundations upon which companies can innovate, differentiate and compete, we can move further, faster. 

Automotive: Driving Toward Production

Automotive has been one of TRISTAN's flagship application domains, and OpenHW processors featured throughout.

NXP's SDR Platform

NXP's software-defined radio prototype uses the CV32E40X processor as the heart of its embedded platform. The demonstrator showcases how open RISC-V processors can support next-generation wireless communication systems for automotive applications.

Importantly, this work does not end with TRISTAN. The platform will continue into the Rigoletto project, underscoring how investments made during TRISTAN continue to generate value beyond a single programme.

Bosch's Radar AI Accelerator

Bosch's demonstrator is one of the project's most sophisticated examples of OpenHW technology in action. The platform combines the CVA6 application processor with a dedicated accelerator connected through the CV-X-IF custom instruction interface. This demonstrates one of RISC-V's greatest strengths: application-specific acceleration without sacrificing software compatibility.

Bosch also contributed significant architectural improvements back to OpenHW, including a new real-time configuration of CVA6 featuring tightly coupled memories (TCMs) and a peripheral bus. These enhancements are now available through the OpenHW GitHub repositories for the wider community.

Perhaps the clearest indication of the platform's maturity is Bosch's long-term ambition: taking CVA6 into a production automotive system including ISO 26262 functional safety qualification.

Connected Automotive Computing

TRISTAN partners aicas and SYSGO showcased another important automotive capability with a CVA6-based FPGA platform supporting cloud-connected vehicle workloads.

Modern vehicles increasingly depend on secure connectivity for diagnostics, software updates and fleet management. By demonstrating these capabilities on an OpenHW platform, they showed that open processor IP can support not only embedded control, but also the wider software ecosystem required for software-defined vehicles.

Their work was presented at the 2026 RISC-V Summit Europe in the paper Bringing Cloud-Connected Automotive Workloads to RISC-V: A CVA6-Based FPGA Case Study, highlighting the growing maturity of OpenHW technology for automotive software platforms.

Industrial and Aerospace

Leonardo demonstrated the flexibility of the CORE-V ecosystem by deploying OpenHW processors across multiple industries. Its industrial demonstrator simulator combines the CV32E40P with the PLiNIO framework and MATCH AI optimisation toolchain, enabling efficient deployment of AI workloads for industrial applications. 

AI at the Edge

Artificial intelligence is another area where OpenHW technology played a significant role.

Battery powered wearable products with the ability to run Linux within a few tens of mW power budget, are important application areas for embedded processors. This goes along with the need to have an inexpensive and power-efficient memory interface at hand for edge-AI needs. The WearGreen demonstrator was designed as a chip in 22nm technology by CEA together with Antmicro and TU Darmstadt. On this chip, an as-open-source-as-possible LPDDR4X memory PHY and controller was co-integrated with a CVA6 processor together with the OpenHW HPDcache, providing a high-performance memory subsystem for demanding AI workloads at the edge. 

The project successfully completed tape-out earlier this year, with silicon expected shortly. 

Communications and Signal Processing

TRISTAN also showcased the versatility of OpenHW processors in communications applications. Semify selected the CV32A60X processor for its SmartWave demonstrator, accelerating decompression of digital waveforms for advanced communications systems. Meanwhile, Yongatek integrated a CV32E40P processor into its eFPGA-based SoC platform, demonstrating how OpenHW cores can be combined with reconfigurable logic to create highly adaptable embedded systems. Yongatek's work contributes to the project's broader goal of creating reusable open hardware components that can be easily integrated into future designs.

Functional Safety Research

OpenHW processors are equally important for next-generation safety technologies. Sysgo extended CV32A6 with a TIP interface for the TraceFS demonstrator from Fraunhofer and Accemic, which showcased advanced trace and functional safety technologies that are essential for automotive and industrial certification. Alongside Bosch's work toward ISO 26262 qualification, projects like TraceFS help build the ecosystem needed to bring open source processors into safety critical applications.

Through TRISTAN, SYSGO also successfully ported the PikeOS Type-1 hypervisor and the ELinOS embedded Linux distribution to the open-source CVA6 core, marking a major milestone for safety-critical RISC-V applications. PikeOS provides the strict real-time separation and security foundations necessary for certifiable industrial workloads, while ELinOS brings the broad flexibility of Linux to the system's partitions. Running this commercial-grade software stack on the CVA6 demonstrates that Europe's open RISC-V ecosystem is rapidly maturing, proving it will be ready for real-world industrial applications.

Alongside, Accemic’s C-Trace is a fully open-source RISC-V trace ecosystem that bundles a Nexus (N-Trace) encoder in SystemVerilog, a reference decoder, an architecture-agnostic trace export format (CTXP), an FPGA demonstrator with an integrated RISC-V CPU, and a TSN/Ethernet Trace-Link IP – the essential ingredients needed to get real, standards-based trace off a RISC-V core. 

Looking Ahead

TRISTAN marked a pivotal advancement in European RISC-V, and it was only just the beginning for open silicon on the Continent. Several project demonstrators are already evolving into follow-on projects, including as part of the EU-funded Rigoletto project. Meanwhile, OpenHW is invested in stewarding the Unified RISC-V IP Access Platform, to collate and promote EU RISC-V IP for every interested party to adopt. 

 

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